1. Technical Field
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a metal wiring layer in a semiconductor device through a dual damascene process.
2. Description of Related Art
As the integration density of semiconductor devices increases, a gap width between metal wiring layers in the semiconductor devices decreases. Consequently, it has been necessary to design metal wiring layers having a multi-layered wiring structure. However, parasitic resistance and capacitance existing between adjacent metal wiring layers in a lateral direction or in a vertical direction may effect the performance of the semiconductor devices.
Such parasitic resistance and capacitance components in a metal wiring layer generally cause a decrease in the operating speed, and thus deteriorate the electrical characteristics of the device. Further, the parasitic resistance and capacitance components increase the total power consumption of chips in the semiconductor device and an amount of signal leakage. Accordingly, a need exists to develop a method for forming a multi-layered wiring layer having low parasitic resistance and capacitance in a super-highly integrated semiconductor device.
Typically, a multi-layered wiring structure that has low parasitic resistance and capacitance is formed of a metal having low specific resistance or a dielectric layer having a low dielectric constant. For instance, a metal wiring layer that is formed of a material having low specific resistance such as copper has been studied. It is difficult to form a copper wiring layer by patterning copper using photolithography. Thus, a dual damascene process is commonly used to form such a copper wiring layer.
FIGS. 1 through 5 are cross-sectional views of a metal wiring layer in a semiconductor device formed according to a conventional method. Referring to FIG. 1, a stopper layer 104 is formed on a semiconductor substrate 100, on which a predetermined conductive layer 102 has been formed. An interlayer insulating layer 106 is formed on the stopper layer 104. Next, a first photoresist pattern 108 is formed on the interlayer insulating layer 106. The first photoresist pattern 108 comprises a first opening H1 having a first width W1 and partially exposing the surface of the interlayer insulating layer 106. In other words, the interlayer insulating layer 106 is covered with photoresist, and then the photoresist is exposed to light and developed, thereby forming the first photoresist pattern 108.
Referring to FIG. 2, the interlayer insulating layer 106 is etched using the first photoresist pattern 108 as an etching mask until the top surface of the stopper layer 104 is exposed. Thus, a via hole 110 having the first width W1 is formed in an interlayer insulating layer 106a. The first photoresist pattern 108 is removed by a conventional method such as an ashing process.
Referring to FIG. 3, a second photoresist pattern 112 is formed on the interlayer insulating layer 106a having the via hole 110. The second photoresist pattern 112 comprises a second opening H2 having a second width W2 greater than the first width W1 and partially exposing the surface of the interlayer insulating layer 106a. The second opening H2 is aligned with the via hole 110.
Referring to FIG. 4, the interlayer insulating layer 106a is etched using the second photoresist pattern 112 as an etching mask by a dry etching method. As a result, a wiring region 114 having the second width W2 is formed in an interlayer insulating layer 106b, and a via hole 110a having the first width W1 is formed at the lower part of the wiring region 114 to connect the conductive layer 102 to the wiring region 114. However, during the etching process of the interlayer insulating layer 106a, the stopper layer 104 may be etched with the interlayer insulating layer 106a, thereby exposing the conductive layer 102.
Even though the interlayer insulating layer 106b has a high etching selectivity to a stopper layer 104a, the stopper layer 104 exposed through the via hole 110 (See FIG. 3) is inevitably etched at a predetermined speed during the etching of the interlayer insulating layer 106a. Accordingly, after etching of the interlayer insulating layer 106b is completed, the exposed stopper layer 104 may be completely etched, and thus the conductive layer may be exposed to an etching atmosphere. If the conductive layer 102, for example, a copper wiring layer, is exposed to an etching atmosphere, hard polymer (not shown) is formed along sidewalls of the interlayer insulating layer 106b. Such hare polymer is difficult to remove. The hard polymer is more easily formed for a case where the interlayer insulating layer 106a to be etched is deeper, the stopper layer 104a is thinner, and the etching selectivity of the stopper layer 104a with respect to the interlayer insulating layer 106b is smaller.
Referring to FIG. 5, the second photoresist pattern 112 is removed by an ashing process. The ashing process uses an oxygen-based plasma. During the removal of the second photoresist pattern 112, that is, during the ashing process, the exposed conductive layer 102 may react with oxygen and form a metal oxide layer 116. The metal oxide layer 116 rapidly increases electrical resistance. Thus, even though the wiring region 114 and the via hole 110a are filled with a conductive material, a metal wiring layer (not shown) and the conductive layer 102 cannot be electrically connected to each other, thus causing a lifting phenomenon. Further, since the ashing process using an oxygen-based plasma is performed after forming the wiring region 114 and the via hole 110a, the process may damage to the surface of the interlayer insulating layer 106b. For instance, H2O, OH, CO2, and H2 released during the ashing process stick to the surface of the interlayer insulating layer 106b, and thus the dielectric constant of the interlayer insulating layer 106b may be rapidly increased.
FIGS. 6 through 10 are cross-sectional views of another metal wiring layer in a semiconductor device formed according to another conventional method. Referring to FIG. 6, a stopper layer 204 is formed on a semiconductor substrate, on which a conductive layer 202 has been formed. An interlayer insulating layer 206 is formed on the stopper layer 204. Next, a first photoresist pattern 208, which includes a first opening H1 having a first width W1 and partially exposing the surface of the interlayer insulating layer 206, is formed on the interlayer insulating layer 206. In other words, the interlayer insulating layer 206 is covered with photoresist, and then the photoresist is exposed to light and developed, thereby forming the first photoresist pattern 208.
Referring to FIG. 7, the interlayer insulating layer 206 is partially etched using the first photoresist pattern 208 as an etching mask so that a partial via hole 210 having the first width W1 is formed in an interlayer insulating layer 206a. The first photoresist pattern 208 is removed by a typical method such as an ashing process.
Referring to FIG. 8A, a second photoresist pattern 212 is formed on the interlayer insulating layer 206a having the partial via hole 210. The second photoresist pattern 212 comprises a second opening H2 having a second width W2 greater than the first width W1 and partially exposing the surface of the interlayer insulating layer 206a. The second opening H2 is formed to be aligned with the partial via hole 210. However, photoresist from the second photoresist pattern 212 may remain on the bottom surface of the partial via hole 210 during the forming of the second photoresist pattern 212 on the interlayer insulating layer 206a. Since the remaining photoresist will act as a barrier to a subsequent etching process of the interlayer insulating layer 206a, an unopened via hole may be formed after etching the interlayer insulating layer 206a. 
FIG. 8B illustrates an exemplary misaligned second photoresist pattern 212a. In this case, photoresist may also remain on the bottom surface of the partial via hole 210 as shown in FIG. 8A.
Referring to FIG. 9a, the interlayer insulating layer 206a is etched using the second photoresist pattern 212 as an etching mask by a dry etching method. As a result, a wiring region 214 having the second width W2 is formed in the interlayer insulating layer 206b, and a via hole 210a having the first width W1 is formed under the wiring region 214 so as to connect the conductive layer 202 to the wiring region 214. However, the photoresist remaining on the bottom surface of the partial via hole 210 of FIG. 8A acts as a barrier to the etching process of the interlayer insulating layer 206a. Thus, the interlayer insulating layer 206b positioned under the partial via hole 210 of FIG. 8A cannot be etched, and thus the via hole 210a may not expose the conductive layer 202.
FIG. 9B illustrates the semiconductor substrate 200 on which the mis-aligned second photoresist pattern 212a is formed. The wiring region 214 and the via hole 210a are formed by etching the interlayer insulating layer 206a using the misaligned second photoresist pattern 212a as an etching mask. As shown in FIG. 9B, if a second photoresist pattern is misaligned, the width of the via hole 211a is less than the first width W1, and the profile of the via hole 291a is deteriorated. As described above with reference to FIG. 9A, if photoresist from the mis-aligned second photoresist pattern 212a remains on the bottom surface of the partial via hole 210 (as shown in FIG. 9B), a via hole (not shown) that does not expose the conductive layer 202 may be formed.
FIG. 10A is illustrates an exemplary metal wiring layer having an unopened via hole. Referring to FIGS. 9A and 10A, the second photoresist pattern 212 is removed by an ashing process. At this time, the photoresist remaining on the bottom surface of the via hole 210a of FIG. 9A is also removed. However, as described above, since the via hole 210 does not expose the conductive layer 202 because of the photoresist remaining on the bottom surface of the via hole 210a of FIG. 9A, the via hole 210a cannot connect the wiring region 214 to the conductive layer 202. Further, since the ashing process is performed using an oxygen-based plasma after forming the wiring region 214 and the via hole 210a, the process may damage to the surface of the interlayer insulating layer 206b. In other words, H2O, OH, CO2, and H2 released during the ashing process may stick to the surface of the interlayer insulating layer 206b, and thus the dielectric constant of the interlayer insulating layer 206b may increase rapidly.
FIG. 10B illustrates the semiconductor substrate 200 after the misaligned second photoresist pattern 212a is removed. As shown in FIG. 10B, the via hole 210a having a width less than the first width W1 is formed, thereby deteriorating the profile of the via hole 210a. Further, when, as described above, photoresist from the mis-aligned second photoresist pattern 212a remains on the bottom surface of the partial via hole 210 (as shown in FIG. 8B), an unopened via hole (not shown) is formed, thereby disconnecting the wiring region 214 and the conductive layer 202.